Programming method for nonvolatile memory device

ABSTRACT

A programming method for a nonvolatile memory device includes inputting least significant bit (LSB) data and most significant bit (MSB) data to each of different latches of a page buffer and in the state in which the LSB data and the MSB data have been inputted to the page buffer, performing a programming operation until threshold voltages of selected memory cells reach a target voltage on the basis of the LSB data and the MSB data.

CROSS-REFERENCE TO RELATED APPLICATION

Priority is claimed to Korean patent application number 10-2009-0135621filed on Dec. 31, 2009, the entire disclosure of which is incorporatedby reference herein.

BACKGROUND

Exemplary embodiments relate to a programming method for a nonvolatilememory device and, more particularly, to a programming method of anonvolatile memory device which is capable of reducing the time that ittakes to perform a programming operation.

A nonvolatile memory device includes a memory cell array in which datais stored, a page buffer for program, erase, and read operations, and anI/O circuit unit for providing a data I/O path to the page buffer forthe data I/O of the memory cell array. The memory cell array includes aplurality of memory cells coupled between word lines and bit lines. Thepage buffer includes a plurality of latches.

A programming operation is described below with reference to theconstruction of the nonvolatile memory device.

When a program command is received, least significant bit (hereinafterreferred to as ‘LSB’) data is inputted to the latch of the page buffer.An LSB programming operation is performed on selected memory cells onthe basis of the LSB data inputted to the latch. In the LSB programmingoperation, the selected memory cells are programmed until thresholdvoltages of the selected memory cells reach a temporary voltage lowerthan a target voltage. After the LSB programming operation is completed,a command for a most significant bit (hereinafter referred to as ‘MSB’)programming operation is received. MSB data is inputted to the latch ofthe page buffer. The MSB programming operation is performed on theselected memory cells on the basis of the MSB data inputted to thelatch. The MSB programming operation is performed until thresholdvoltages of the selected memory cells reach the target voltage.

In the above programming operations, after the LSB data is inputted andthe LSB programming operation is performed, the MSB data is inputted andthe MSB programming operation is performed. Accordingly, the time thatit takes to perform the entire programming operation is long.

BRIEF SUMMARY

Exemplary embodiments relate to a programming method of a nonvolatilememory device, which is capable of reducing the time that it takes toperform the entire programming operation by performing LSB and MSBprogramming operations after both LSB data and MSB data are inputted topage buffers.

A programming method of a nonvolatile memory device according to anaspect of the present disclosure includes inputting least significantbit (LSB) data and most significant bit (MSB) data to different latchesof a page buffer. When the LSB data and the MSB data have been inputtedto the page buffer, a programming operation is performed until thresholdvoltages of selected memory cells reach a target voltage on the basis ofthe LSB data and the MSB data.

A programming method for a nonvolatile memory device according toanother aspect of the present disclosure includes inputting MSB data toa first latch of a page buffer and LSB data to a second latch,performing an LSB programming operation on selected memory cells usingthe LSB data, and performing an MSB programming operation on theselected memory cells using the MSB data.

According to yet another aspect of the present disclosure, there isprovided a programming method for a nonvolatile memory device comprisinga page buffer including first and second latches. LSB data is inputtedto the first latch, sending the LSB data of the first latch to thesecond latch, inputting MSB data to the first latch, performing an LSBprogramming operation until threshold voltages of selected memory cellsreach a second target voltage using the LSB data of the second latch,and performing an MSB programming operation until threshold voltages ofthe selected memory cells reach a first target voltage or a third targetvoltage using the MSB data of the first latch.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart illustrating a programming method for anonvolatile memory device according to an exemplary embodiment of thisdisclosure;

FIG. 2 is a schematic block diagram of a nonvolatile memory deviceillustrating the programming method according to this disclosure;

FIG. 3 is a diagram illustrating the states of memory cells according tothreshold voltages; and

FIG. 4 is a block diagram illustrating a programming method of anonvolatile memory device according to an exemplary embodiment of thisdisclosure.

DESCRIPTION OF EMBODIMENTS

Hereinafter, some exemplary embodiments of the present disclosure willbe described in detail with reference to the accompanying drawings. Thefigures are provided to allow those having ordinary skill in the art tounderstand the scope of the embodiments of the disclosure.

FIG. 1 is a flowchart illustrating a programming method for anonvolatile memory device according to an exemplary embodiment of thisdisclosure.

When a programming process is started, an address for LSB programming isinputted in response to a program command at step S01. LSB data isinputted to the first latch of a page buffer at step S02. The LSB datainputted to the first latch is sent to the second latch of the pagebuffer at step S03. An address for MSB programming is inputted inresponse to the program command at step S04. MSB data is inputted to thefirst latch at step S05. Consequently, the MSB data is stored in thefirst latch of the page buffer, and the LSB data is stored in the secondlatch thereof.

An LSB programming operation is performed on selected memory cells usingthe LSB data stored in the second latch at step S06. For example, a casewhere a memory cell becomes an erase state, a first programming state, asecond programming state, or a third programming state according to alevel of the threshold voltage of the memory cell is described. Here,the LSB programming operation is performed to raise all the thresholdvoltages of memory cells to be programmed with the second and thirdprogramming states up to a target voltage of the second programmingstate.

When all the threshold voltages of the memory cells to be programmedwith the second and third programming states reach the target voltage ofthe second programming state, the LSB programming is terminated. Next,an MSB programming operation is performed on the selected memory cellsusing the MSB data stored in the first latch at step S07. Moreparticularly, the MSB programming operation is performed until all thethreshold voltages of memory cells to be programmed with the first andthird programming states reach the target voltage.

When all the threshold voltages of the selected memory cells reach thetarget voltage, all the programming operations are terminated.

FIG. 2 is a schematic block diagram of a nonvolatile memory deviceillustrating the programming method according to this disclosure.

The programming method described with reference to FIG. 1 is describedbelow with reference to the schematic block diagram of the nonvolatilememory device.

Referring to FIG. 2, the nonvolatile memory device includes a memorycell array 100 for storing data, a page buffer PB for storing data to beprogrammed and outputting a programming operating voltage according tothe stored data to be programmed, and an I/O circuit unit 110 forproviding a data I/O path to the page buffer PB for the data I/O of thememory cell array 100.

It is to be noted that only one page buffer PB and only a first latch L1and a second latch L2, from among a plurality of circuits constitutingthe page buffer PB, are shown in order to simply describe theprogramming method according to this disclosure.

The programming method is described below in detail.

An address including an LSB address is inputted. LSB data outputted fromthe I/O circuit unit 110 is inputted to the first latch L1 in responseto an input signal IO (INPUT). The LSB data inputted to the first latchL1 is sent to the second latch L2 (TRAN). Next, an address including anMSB address is inputted. MSB data outputted from the I/O circuit unit110 is inputted to the first latch L1 in response to the input signal IC(INPUT). Accordingly, both the MSB data and the LSB data are stored inthe page buffer PB.

LSB programming is performed on selected memory cells included in thememory cell array 100 using the LSB data stored in the second latch L2(LSG PGM). After the LSB programming is completed, MSB programming isperformed on the selected memory cells of the memory cell array 100using the MSB data stored in the first latch L1.

FIG. 3 is a diagram illustrating the states of memory cells according tothreshold voltages, and FIG. 4 is a block diagram illustrating aprogramming method for a nonvolatile memory device according to anexemplary embodiment of this disclosure.

Referring to FIG. 3, the memory cells are classified into differentstates according to their threshold voltages. For example, memory cellshaving negative (−) threshold voltages are in an erase state ER STATE.Memory cells having positive (+) threshold voltages at the lowest levelare in a first program state P1 STATE. Memory cells having thresholdvoltages higher than the first program state are in a second programstate P2 STATE. Memory cells having threshold voltages higher than thesecond program state are in a third program state P3 STATE.

If LSB data LSB DATA is “1” and MSB data MSB DATA is “1”, it may bedefined as the erase state ER STATE. According to the same datasequence, “10” may be defined as the first program state P1 STATE, “01”may be defined as the second program state P2 STATE, and “00” may bedefined as the third program state P3 STATE.

A method of programming memory cells with different states is describedbelow with reference to FIG. 4. It is to be noted that only four pagebuffers PB1 to PB4 are shown in order to program the memory cells withthe four states (ER STATE and P1 to P3 STATES of FIG. 3).

Referring to FIG. 4, the nonvolatile memory device includes a memorycell array 100 for storing data, the first to fourth page buffers PB1 toPB4 for storing data to be programmed and outputting a programmingoperating voltage on the basis of the stored data to be programmed, andan I/O circuit unit 110 for inputting the data to be programmed to thefirst to fourth page buffers PB1 to PB4 or outputting the data.

For example, a case where data “11” for maintaining a memory cell to theerase state ER STATE is inputted to the first page buffer PB1 and anyone of data “01” for programming memory cells with the first programmingstate P1 STATE, data “10” for programming the memory cells with thesecond programming state P2 STATE, and data “00” for programming thememory cells with the third programming state P3 STATE is inputted tothe second to fourth page buffers PB2 to PB4 is described below.

When a programming process is started, LSB data outputted from the I/Ocircuit unit 110 is inputted to the first latches L1 of the first tofourth page buffers PB1 to PB4. More particularly, data “1” is inputtedto the first latches L1 of the first and second page buffers PB1 andPB2, and data “0” is inputted to the first latches L1 of the third andfourth page buffers PB3 and PB4.

The LSB data stored in the first latches L1 of the first to fourth pagebuffers PB1 to PB4 are sent to the second latches L2 of the first tofourth page buffers PB1 to PB4. Accordingly, the same data as stored inthe first latches L1 of the first to fourth page buffers PB1 to PB4 arestored in the second latches L2 of the first to fourth page buffers PB1to PB4.

Next, MSB data outputted from the I/O circuit unit 110 is inputted toall the first latches L1 of the first to fourth page buffers PB1 to PB4.Accordingly, both the MSB data and the LSB data are stored in the firstto fourth page buffers PB1 to PB4. More particularly, data “1” (MSBdata) is stored in the first latch L1 of the first page buffer PB1, data“1” (LSB data) is stored in the second latch L2 of the first page bufferPB1. Data “0” (MSB data) is stored in the first latch L1 of the secondpage buffer PB2, and data “1” (LSB data) is stored in the second latchL2 of the second page buffer PB2. Data “1” (MSB data) is stored in thefirst latch L1 of the third page buffer PB3, and data “0” (LSB data) isstored in the second latch L2 of the third page buffer PB3. Data “0”(MSB data) is stored in the first latch L1 of the fourth page bufferPB4, and data “0” (LSB data) is stored in the second latch L2 of thefourth page buffer PB4.

An LSB programming operation is performed on selected memory cellsincluded in the memory cell array 100 on the basis of the LSB datastored in the second latches L2 of the first to fourth page buffers PB1to PB4.

More particularly, a bit line BL is discharged or is precharged to aprogram-inhibition voltage on the basis of LSB data stored in the secondlatch L2. For example, in case where the LSB data stored in the secondlatch L2 is “1”, the bit line BL is precharged to a program-inhibitionvoltage (e.g., Vcc) level. Meanwhile, in case where the LSB data storedin the second latch L2 is “0”, the bit line BL is discharged (e.g.,Vss). That is, when the LSB programming operation is performed, thethreshold voltages of memory cells coupled to the first and second pagebuffers PB1 and PB2 maintain the erase state (ER STATE of FIG. 3), andthe threshold voltages of memory cells coupled to the third and fourthpage buffers PB3 and PB4 are raised. The LSB programming operation isperformed until all the threshold voltages of memory cells coupled tothe third and fourth page buffers PB3 and PB4 reach a second targetvoltage (that is, a target voltage of the second program state P2STATE). During the LSB programming operation, an LSB programmingverification operation is performed using the second latch L2.

After the LSB programming is completed, the memory cells coupled to thefirst and second page buffers PB1 and PB2 maintain the erase state ERSTATE, and the memory cells coupled to the third and fourth page buffersPB3 and PB4 become the second programming state P2 STATE.

Next, an MSB programming operation is performed. The MSB programmingoperation is performed on the basis of the MSB data stored in the firstlatches L1 of the first to fourth page buffers PB1 to PB4.

More particularly, the bit line BL is discharged or is precharged to aprogram-inhibition voltage on the basis of the MSB data stored in thefirst latch L1. For example, in case where the MSB data stored in thefirst latch L1 is “1”, the bit line BL is precharged to aprogram-inhibition voltage (e.g., Vcc) level. Meanwhile, in case wherethe MSB data stored in the first latch L1 is “0”, the bit line BL isdischarged (e.g., Vss). That is, when the MSB programming operation isperformed, the memory cells coupled to the first and third page buffersPB1 and PB2 maintains the state at the time of the LSB programmingoperation, and the memory cells coupled to the second and fourth pagebuffers PB2 and PB4 are programmed so that threshold voltages thereofreach respective target voltages.

More particularly, in the MSB programming operation, the memory cellcoupled to the first page buffer PB1 maintains the erase state ER STATE,and the memory cell coupled to the third page buffer PV3 maintains thesecond program state P2 STATE. In the MSB programming operation, thememory cell coupled to the second page buffer PB2 is programmed so thata threshold voltage thereof reaches a first target voltage (that is, atarget voltage of the first program state P1 STATE), and the memory cellcoupled to the fourth page buffer PB4 is programmed until a thresholdvoltage thereof reaches a third target voltage (that is, a targetvoltage of the third program state P3 STATE). During the MSB programmingoperation, an MSB programming verification operation is performed usingthe first latch L1.

When all the threshold voltages of the memory cells coupled to thesecond and fourth page buffers PB2 and PB4 reach the target voltages ofthe first programming state P1 STATE and the third programming state P3STATE, the entire programming operation is terminated.

As described above, in this disclosure, a programming operation forraising the threshold voltages of memory cells to be programmed with thesecond or third program state P2 STATE or P3 STATE to a temporaryvoltage lower than a target voltage is not performed. Accordingly, thetime that it takes to perform the entire programming operation can bereduced.

In accordance with this disclosure, in a programming operation, LSB andMSB programming operations are performed in the state in which both LSBdata and MSB data have been inputted to the page buffers. Accordingly,the time that it takes to perform the entire programming operation canbe reduced.

1. A programming method of a nonvolatile memory device, comprising:inputting least significant bit (LSB) data and most significant bit(MSB) data to different latches of a page buffer; and performingsequentially an LSB programming operation and an MSB programmingoperation on the basis of the LSB data and the MSB data.
 2. Theprogramming method of claim 1, wherein the programming operationcomprises performing a first programming operation and a firstverification operation on the basis of the LSB data and then performinga second programming operation and a second verification operation onthe basis of the MSB data.
 3. The programming method of claim 1, whereinthe LSB programming operation and the MSB programming operation areperformed until threshold voltages of selected memory cells reach atarget voltage.
 4. The programming method of claim 1, wherein the LSBdata and the MSB data are in the state in which the LSB data and the MSBdata have been inputted to the page buffer.
 5. A programming method of anonvolatile memory device, comprising: inputting MSB data to a firstlatch of a page buffer and LSB data to a second latch of the pagebuffer; performing an LSB programming operation on selected memory cellsusing the LSB data; and performing an MSB programming operation on theselected memory cells using the MSB data.
 6. The programming method ofclaim 5, wherein inputting the LSB data and an MSB data comprises:inputting the LSB data to the first latch; sending the LSB data of thefirst latch to the second latch; and inputting the MSB data to the firstlatch.
 7. The programming method of claim 5, wherein the LSB programmingoperation is performed to program the selected memory cells on the basisof the LSB data stored in the second latch.
 8. The programming method ofclaim 5, wherein the MSB programming operation is performed to programthe selected memory cells on the basis of the MSB data stored in thefirst latch.
 9. A programming method of a nonvolatile memory devicecomprising a page buffer including first and second latches, theprogramming method comprising: inputting LSB data to the first latch;sending the LSB data of the first latch to the second latch; inputtingMSB data to the first latch; performing an LSB programming operationuntil threshold voltages of selected memory cells reach a second targetvoltage using the LSB data of the second latch; and performing an MSBprogramming operation until threshold voltages of the selected memorycells reach one of a first target voltage and a third target voltageusing the MSB data of the first latch.
 10. The program method of claim9, wherein: the first target voltage is lower than the second targetvoltage, and the second target voltage is lower than the third targetvoltage.
 11. The programming method of claim 9, wherein unselectedmemory cells maintain an erase state in the LSB programming operation.12. The program method of claim 9, wherein the LSB programming operationis performed such that memory cells to be programmed to have thresholdvoltages equal to the third target voltage reach the second targetvoltage.
 13. The programming method of claim 9, wherein the MSBprogramming operation is performed until threshold voltages of memorycells, selected from among memory cells of an erase state, reach thefirst target voltage and until threshold voltages of memory cells,selected from among memory cells programmed to have threshold voltagesequal to the second target voltage reach the third target voltage. 14.The programming method of claim 9, wherein during the LSB programmingoperation, an LSB programming verification operation is performed usingthe second latch.
 15. The programming method of claim 9, wherein duringthe MSB programming operation, an MSB programming verification operationis performed using the first latch.